This invention generally relates to a dynamic random access memory (DRAM), and more particularly to a method of hiding a refresh operation in a DRAM or in an embedded DRAM used for constructing a system on a chip or in an electric system.
CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumer applications. Today multimedia requires at least a 64 MB and preferably even a 128 MB memory, which increases the relative cost of the memory system within a computer. In the near future, it is likely that 256 MB and 512 MB computers will become commonplace, which suggests a potential strong demand for 256 Mb DRAMs and beyond. Still in the development stage, DRAMs in the Gigabit range are already under way. As DRAM density and the lithographic difficulties increase, it becomes more difficult to have a fully functional DRAM. This necessitates the introduction of new techniques that guarantee a reasonable chip yield of the product notwithstanding the added complexity of the design and manufacture of such memory devices. Process engineers are continuously attempting to reduce and, ultimately, eliminate mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs and, more specifically, redundancy replacement.
A typical DRAM features a single transistor cell. Because of its simplicity, the DRAM cell size is ⅙ that of a conventional six-transistor cell commonly used in a static random access memory (SRAM), which is best suited for a high density memory. Such a memory, however, requires to be periodically refreshed in order to preserve the data stored therein. Typically, in most electric systems, the refresh operation is managed by a memory controller. However, the refresh operation for DRAMs delays the time for command executions in the electric system. Less frequent refresh operations are important to increase the electric system availability for the command executions. However, it is difficult to guarantee a reasonable availability of the electric system in the future because the number of refresh cycles grows as the DRAM density increases. In addition to the availability problem for high density DRAMs, future Systems-on-Chip (SOC) use various embedded DRAMs (eDRAMs), each of which requiring its own refresh management. However, having its own refresh management is expensive. Furthermore, the eDRAM retention time in a SOC is generally considerably smaller than the retention time of a standard DRAM because of higher temperature requirements, wider voltage variations, and logic compatible process technology restrictions. If the retention time is poor, refreshing the memory cells further reduces the electric system availability. Thus, there exists a strong potential need for providing a method for concealing a refresh operation for high density DRAMs and eDRAMs by way of self- refresh management.
FIG. 1 shows a schematic block representation of a DRAM used to illustrate a conventional method of partially hiding a refresh operation. A DRAM chip or macro (100) is shown consisting of two DRAM arrays (110A and 110B). When the DRAM is addressed, either array 110A or array 110B is enabled to activate a wordline (WL). Because only one of the two arrays (110A and 110B) are used for accessing, the second array can execute the refresh operation while the first array is used for executing electric system commands. By way of example, WLi in array 110A is enabled by an access command. During the access command execution with WLi in array 110A, any wordlines (e.g., WLj) in 110B simultaneously perform the refresh operation. It is not possible, however, to refresh other wordlines (e.g., WLk) in the array 100A as long as WLi is continuously accessed. Thus, the prior art limits the refreshing operation to a subset of DRAM cells, and fails to provide the necessary additional refresh capabilities needed to guarantee data retention for all the memory cells.
FIG. 2 shows a second conventional approach of concealing a refresh. A DRAM chip or macro (200) is shown consisting of two DRAM arrays (210A and 210B). The DRAM (200) includes a static random access memory (SRAM) array (220), the size of which is equal or larger than one of the two DRAM arrays. When WLi in DRAM array (210A) is activated, the data bits in the DRAM array (210A) are copied to the cells coupled to WLixe2x80x2 in the SRAM array (220). Similar to the first method described with reference to FIG. 1, WLj in array (210B) is refreshed while WLi in the DRAM array (210A) performs the access operation. The corresponding process depends whether or not the data bits reside in the SRAM or in the DRAM array. The DRAM array needs to be accessed for the corresponding memory access execution when the data bits do not reside in the SRAM array. However, this command execution also allows the data bits to be copied from the DRAM array to the SRAM array. Thus, for the next memory access execution with the corresponding address, it is not necessary to access the DRAM array because the data bits reside in the SRAM array. If the data bits reside in the SRAM array, the data bits are read from or written directly into other SRAM arrays and, therefore, the DRAM array may be refreshed during the SRAM array access operation. A user may continuously access the DRAM array by accessing different wordlines within one array, (e.g., 210A). At the end of this operation, all the data bits in array (210A) will be copied to the SRAM, freeing the following cycles for refreshing the cells in the corresponding DRAM array (i.e., 210A). This technique enables a fully compatible SRAM protocol within the DRAM technology. However, this approach is not suited for small or medium size DRAMs because having an additional SRAM array is expensive.
FIGS. 3A-3B illustrate a third conventional method for concealing a refresh operation. Unlike previous techniques, two-transistor cells (2T) are preferably used. A capacitor (CAP) is read (or written into) by either transistor A (TRA) or transistor B (TRB). This makes it possible to use TRA and TRB, respectively, for accessing and refreshing purposes. FIG. 3A shows an array configuration wherein each cell uses two wordlines (WLA and WLB) and two pairs of bitlines (BLA and BLB) supported by sense amplifiers (SAA and SAB). This enables a differential sensing scheme with an adjacent bitline pair (e.g., BLA and {overscore (BLA)}) in the same array (folded bitline architecture). However, 2T cells require twice as many BLs and twice as many WLs, resulting in a fourfold increase in the size of the cells. FIG. 3B shows an array configuration, wherein each cell uses two wordlines (WLA and WLB). A differential sensing scheme is realized by utilizing a bitline pair (e.g., BLA and {overscore (BLA)}) in different arrays (open bitline architecture). This architecture reduces the number of bitlines to the same number of a conventional array arrangement consisting of only 1T cells. This results in only doubling the size of the cell. However, the area penalty is still large.
Accordingly, it is an object of the present invention to hide a refresh operation in a DRAM or eDRAM.
It is another object to hide the refresh operation in a DRAM or eDRAM by concurrently reducing the internal random access cycle time with respect to the external random access cycle time
It is a further object to hide the refresh operation in a DRAM or eDRAM using an interlocked method.
It is still another object to hide the refresh operation in a memory device without invoking special refresh commands.
It is yet another object to hide the refresh operation without resorting to a banking configuration.
It is still a further object to hide the refresh operation without resorting to an on-chip cache.
It is a more particular object to hide the refresh operation without substantially increasing the chip size.